The present disclosure relates to the electrical, electronic, and computer arts, and, more particularly, to methods for cutting fins in the fabrication of integrated circuits comprising FinFETs.
Multi-gate field-effect transistors (FETs) are of considerable interest because of their superior electrostatic integrity, as well as their promise of lower supply voltages, reduced threshold voltages, and extended scalability. FinFETs are one form of such multi-gate device. In a FinFET, a narrow channel feature (i.e., fin) is raised above the substrate and passes under a gate, which effectively wraps around the fin. The gate is thereby capacitively coupled to the top as well as the sides of the fin. So structured, very little leakage current passes through channel portions of the fin when the device is in the off state. This allows the use of lower threshold voltages and higher switching speeds. Substrates used to form FinFETs include semiconductor on insulator (SOI) substrates and bulk semiconductor substrates. Silicon fins are formed in some FinFETs on substrates via known technology such as sidewall image transfer (SIT). FinFET structures including SOI substrates can be formed, in part, by selectively etching the crystalline silicon layers down to the oxide or other insulating layers thereof following photolithography. Active fin heights are set by SOI thickness when employing SOI substrates. In bulk FinFETs, active fin height is set by oxide thickness and etched fin height. The gates of FinFETs can be formed using a “gate-first” process wherein a gate stack and spacers are formed prior to selective epitaxial growth wherein source and drain regions are enlarged. A “gate-last” process may alternatively be employed wherein the source/drain regions are formed immediately following fin patterning. Gate-last procedures can involve making a dummy gate, fabricating other elements of the transistor, removing the dummy gate, and replacing the removed dummy gate with actual gate materials.
A single fin may initially be patterned to span across regions that will ultimately be separated into multiple FinFETs. Later, after forming additional elements such as gates and contacts, the fin may be cut to isolate one transistor from another. Ideally, such cutting will utilize as small an area as possible. Nevertheless, cutting just the fins without simultaneously damaging the nearby structures remains challenging. Gas phase plasmas, for example, may be made somewhat selective to silicon, but have enough plasma potential to also etch nearby dielectric materials. When using bulk substrates in the fabrication of integrated circuits including FinFETs, the fins are cut relatively deeply to ensure a disconnecting fin cut.
Replacement metal gate (RMG) processes employed in “gate last” fabrication techniques may include depositing disposable gate level layers on a semiconductor substrate as blanket layers, i.e., as unpatterned contiguous layers. The disposable gate level layers can include, for example, a vertical stack of a disposable gate dielectric layer, a disposable gate material layer, and a disposable gate cap dielectric layer. The disposable gate level layer(s) can be removed selective to a planarization dielectric layer to be subsequently formed. The disposable gate level layers are lithographically patterned to form disposable gate structures.
Gate spacers can be formed on sidewalls of each of the disposable gate structures, for example, by deposition of a conformal dielectric material layer and an anisotropic etch. Ion implantations and/or epitaxial deposition processes can be employed to form source/drain regions for some devices. For example, dopants can be implanted into portions of the body regions that are not covered by the disposable gate structures and spacers.
A planarization dielectric layer is deposited over the semiconductor substrate, the disposable gate structures, and the gate spacers. The planarization dielectric layer may include a dielectric material that can be planarized, for example, by chemical mechanical planarization (CMP). For example, the planarization dielectric layer can include a doped silicate glass, an undoped silicate glass (silicon oxide), and/or porous or non-porous organosilicate glass. The planarization dielectric layer is planarized above the topmost surfaces of the disposable gate structures.
The disposable gate structures are removed by at least one etch. The removal of the disposable gate structures can be performed employing an etch chemistry that is selective to the gate spacers and to the dielectric materials of the planarization dielectric layer. Cavities are formed from the spaces remaining after the disposable gate structures are removed. The semiconductor surfaces above the channel regions of the substrate can be physically exposed at the bottoms of the gate cavities, though native oxide layers may be present. The gate cavities are laterally enclosed by the gate spacers that were formed on the sidewalls of the disposable structures. Replacement gate structures are ordinarily formed in the gate cavities. Replacement gate structures are formed by replacement of the disposable structures and overlie channel regions of the structures. A gate dielectric and a gate electrode are formed within each of the gate cavities.